The Bandwidth Engine family of ICs utilizes a CEI-11G-SR and XFI compatible interface enabling the first generation devices to operate up to 15 Gbps. The SerDes are tuned for low-power, low-latency transmission over traces of up to 20 cm long. Because existing serial interface standards are optimized for large payloads the transfers are inefficient for the small access quanta that theBandwidth Engine delivers. In order to overcome this issue the Bandwidth Engine SerDes supports the 90% efficient GigaChip Interface protocol to enable high-bandwidth, high-efficiency chip-to-chip communications. The GigaChip Interface also includes an automatic error recovery mechanism in the event of a channel CRC error to guarantee end-to-end data integrity and system reliability.
By utilizing an efficient serial technology, the Bandwidth Engine family is able to deliver significantly more bandwidth per pin, per Watt and per square millimeter of Silicon. The serial interface of the Bandwidth Engine also allows system designers more flexibility during board layout than parallel-based interfaces.
Advantages of MoSys’ High Speed SerDes I/O in the Bandwidth Engine: