Bit Safe® technology provides the ability to transparently detect, remove and replace storage locations which are weaker than the baseline population, thus reducing the risk of an uncorrectable multi-bit error.

Available as an optional feature on all second-generation Bandwidth Engine devices (MSR620, MSR820), Bit Safe functionality offers designers optional capabilities, including:

  • Background BIST
  • Memory Scrubbing
  • Memory Sparing
  • Persistent Self Repair
  • Key Data Protection Features of Bandwidth Engine:

Internal array architecture:

  • 72 bit word – supports ECC
  • ECC check and correct on all Macro operations
  • SEU resistant 1T-SRAM® memory core
  • Bit Safe Self Test and Self Repair

GigaChip® Interface:

  • CRC Protected Serial Link Protocol
  • Automatic Error Recovery Mechanism
  • Host Error Recovery Option