Bandwidth Engine 3 (BE-3) Architecture

The BE-3 architecture was defined to support multi-threaded processor cores with its highly segmented memory array architecture, unprecedented on-chip bandwidth, variable payload size, integrated dynamic scheduler and multi-cycle macro operations. BE-3 supports both deterministic and non-deterministic data return. The Bandwidth Engine 3 datasheet is available under NDA.

Bandwidth Engine 2 (BE-2) Architecture

The BE-2 architecture will continue to deliver the lowest latency and deterministic data access. The three devices offer purpose-built solutions to address specific applications for networking infrastructure equipment manufacturers.

Comparison Table

Architecture BE-1 BE-2 BE-3
Part Number
MSR576 MSR620
MSR622 Burst MSR820
MSR630, MSR830, MSRZ30, MSRS30
Interface GCI +
GCI + TL-1.0 GCI + TL-2.0
Interface Rate 6 – 10G 8 – 12.5G 10 – 28G
Internal Bandwidth 223 Gbps 400 Gbps >1500 Gbps
Transaction Rate 2.75 B 4.5B 10B
Scheduling Host - Calendar Host - Calendar Host Calendar or On-chip
Weighted Dynamic Round Robin
Size 576Mb 576Mb 1Gb
Functions ALU Burst
Single Cycle
Extensive Single and Multi-cycle Macros

Technical Papers

MoSys unveiled its third generation Bandwidth Engine architecture in a presentation entitled "Intelligent Offload Supporting Data Center Equipment at 100G+" at the Linley Tech Data Center Conference 2014 during the Session 3 entitled Advancements in Packet Processing.