Bandwidth Engine 3 (BE-3) and Bandwidth Engine 2 (BE-2) Architecture
MoSys Bandwidth Engine® Family of ICs is a memory solution optimized for transaction performance with serial interfaces. The new Bandwidth Engine 3 Devices accelerate EZchip NPS-400 and high performance FPGAs for Networking, Data Center and Security Applications. These monolithic devices deliver extreme memory and offload performance without requiring exotic packaging with ultra-dense interconnect or complex cooling solutions associated with multi-chip modules. The underlying performance and features which are common between all part types of the 2nd generation and 3rd generation family are:
The device architecture relies on three elements:
The Bandwidth Engine 3 device for EZchip NPS-400 (MSRZ30) is an MSR830 with a GigaChip Interface that is optimized for the data structures and transfer requirements of the EZchip NPS-400 network processor. The addition of the MSRZ30 to the NPS-400 delivers a substantial improvement in memory bandwidth and transaction rate enabling the NPS-400 to increase the packet processing rate.
The NPS-400 can be configured with one or two MSRZ30 devices connected for maximum performance and capacity, or with one or two MSRZ30 that are shared between two NPS-400 to achieve different system level performance points.
The Bandwidth Engine 3 - Macro device (MSR830) adds functionality to the MSR630 by providing the same base capabilities with Intelligent Offload Macros statistics and metering to increase performance and add features for next generation networking and communications equipment.
The MSR830 has several macro enhancements in addition to the macros in the MSR820. The MSR830 supports thirty-two 100GE ports with real time metering and statistics.
The Bandwidth Engine 2 - Macro device (MSR820) can be used to accelerate industry standard Statistics counters and Meters. The MSR820 adds functionality to the MSR622 by providing the same base capabilities with added Intelligent Offload Macros.
MSR820 delivers offload capabilities for functions such as statistics and metering to increase performance and add features for networking and communications equipment. The MSR820 can support real time counters and meters for up to eight 100G ports.
Burst device (MSR630) with onboard domain scheduling maintains write-read data coherency for all accesses similarly to the MSR720. The MSR720 will be lower latency than the MSR630.
The Bandwidth Engine 2 - Access device (MSR720), intended for state applications, can perform simultaneous read-write without bank conflict to any two locations concurrently. The MSR720 caches and schedules write operations and when necessary to maintain coherency will bypass data from cache to output. The MSR720 can be considered to be four QDR SRAMs within the Bandwidth Engine IC.
Burst device (MSR630) enables high rate lookup or high performance buffer capabilities with support for concurrent 400Gbps writes and 400Gbps reads resulting in up to 400Gbps Full Duplex effective data throughput.
The Bandwidth Engine 2 - Burst device (MSR622) enables high rate lookup or high performance buffer capabilities with support for concurrent 200Gbps writes and 200Gbps reads resulting in up to 200Gbps Full Duplex effective data throughput.
|Attribute||Bandwidth Engine Family|
|BE - 2||BE - 3|
|Transaction Rate||4.5 B||> 10 B|
|Throughput (full duplex)||200 Gbps||400 Gbps|
|Capacity||576 Mb||1125 Mb|
|Intelligent Offload Macros||Yes||Yes|
|Deterministic Random Access||Yes||Optional|
|On board scheduling||No||Yes|