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LineSpeed 100G PHYs
LineSpeed 100G PHYs
100G Low Power CDR
100G Quad Retimer
100G Octal Retimer w/ RS-FEC
10-Lane 28G Retimer w/ RS-FEC
100G Multi-Mode Gearbox
100G Gearbox w/ RS-FEC
100G Multi-Link Gearbox (MLG)
Support Tools
 
LineSpeed 100G PHYs

LineSpeed 100G PHYs Enable Flexible Datapaths for Terabit Systems
 

LineSpeed 100G PHY Products

Product Family Product Name Part Number Package Size Video Product Brief
Retimers          
LineSpeed 100G Low Power CDR MSH110 8x8mm MoSys LineSpeed 100G Low Power Retimer Interoperability with Finisar CFP4 at ECOC 2014
100G Quad Retimer MSH210 13x13mm MoSys LineSpeed 100G PHY Hot Swap Test Using Passive Copper Cables
LineSpeed Flex 100G Octal Retimer with FEC MSH221 12x12mm  
10 Lane Full Duplex 25G Retimer with FEC MSH225 17x17mm  
Gearbox          
LineSpeed 100G Multi-Mode Gearbox MSH310 19x19mm Multi-Mode Gearbox Functionality Test
100G Gearbox with RS-FEC MSH320 17x17mm  
LineSpeed Flex 100G Multi-Link Gearbox (MLG) for Modules MSH321 12x12mm  
100G Multi-Link Gearbox (MLG) for Line Cards MSH322 17x17mm  


MSH110 LineSpeed 100G Low Power Octal CDR

The MoSys LineSpeed™ 100G Low Power Octal CDR (MSH110) is a single-chip CMOS IC optimized for CDR/retiming applications inside optical or copper modules that have aggressive power and thermal requirements and can also be used on line cards to support full duplex 100GE or OTN operation. The device supports QSFP28, CFP4 and CFP2 4x25G module interfaces with a strong self-adapting equalizer for ease of connection and improved signal integrity. The device features the industry′s lowest power dissipation, small package footprint, reference-free operation, system and line side integrated loopbacks, and diagnostic capabilities using the MoSys IC Spotlight™ Analyzer in conjunction with on-chip PRBS generation and error checking.

QSFP28 Module Application Example:

Key Features:

  • Industry lowest power and highest integration
    • 100G Full Duplex design (8 lanes)
    • Industry lowest power - 750mW
    • CMOS design
  • Ease of use
    • Self adapting Rx equalization
    • Local and remote loopback
    • Monitor functions and PRBS generation and test capability (all ports)
  • Design flexibility
    • Reference-less option
    • Polarity and lane swap
    • Flexible reference clocks
    • Small 8x8mm package fits all module types

MSH210 LineSpeed 100G Quad Retimer

The LineSpeed 100G Quad Retimer IC (MSH210) is a single chip low power CMOS device designed to support 100 Gigabit IEEE and OIF standards for line card, module, cable or backplane applications in next generation data center, enterprise or service provider networking systems. The device supports up to LineSpeed Flex Gbps serial data with minimum external components and includes equalization to support longer reach applications.

The full duplex device provides equalization, clock and data recovery, and retransmitter for 4 lanes of serial 25 Gbps data in each direction. It supports multiple on chip error checking and monitoring capabilities.

Application Example:

Key Features:

  • Full duplex quad retimer up to 28Gbps
  • Support of IEEE and OIF 100G standards
  • Strong self adapting equalizer - eye opening capability
  • CDR & SerDes functions
  • Transmitter and TX pre-emphasis
  • TPRBS generator and bit error rate checker
  • Low power standard CMOS

MSH221 LineSpeed Flex 100G Octal Retimer with RS-FEC

The LineSpeed Flex 100G Octal Retimer with integrated RS-FEC (MSH221) supports up to 4 full duplex lanes (8 channels) with independent rates up to 28 Gbps for high data rate line card applications up to terabits per second. The flexible, multi-protocol SerDes device includes an option for the Clause 91 RS-FEC specified in 802.3bj for 4x25G NRZ interfaces. When the RS-FEC is turned off, the MSH221 device functions as a standard multi-rate and multi-protocol retimer capable of passing data whether encoded or non-encoded. Each lane is independent and supports a broad range of frequencies compatible with 10G, 25G, 40G and 100G Ethernet and OTN standards. With the 100G 802.3bj RS-FEC encode, decode and correction functions enabled, the device will encode data in one direction and decode and correct data (if needed) in the other direction. The IEEE 802.3bj RS-FEC enables additional signal integrity and/or distance capability over copper or optical interconnects and has been specified in multiple standards and MSAs.

The device provides equalization, clock and data recovery, and retransmitter for up to 8 lanes of serial traffic from 10-15G or 25-28G25 Gbps. It supports multiple on chip error checking and monitoring capabilities, reference clocks and ability to monitor the optional 100G RS-FEC status.

The device is packaged in a small 12x12mm FCCSP for module or daughter card applications. The device is pinout compatible to the MSH221 Octal Retimer with FEC.

Application Example:

Key Features:

  • Full duplex 100G retimer (8 lanes)
  • Includes 802.3bj Clause 91 RS-FEC (4x25.78G)
  • Support of IEEE and OIF 10, 25, 40 and100G standards for Ethernet and OTN
  • Self-adapting equalizer and eye opening capability
  • Transmitter and TX pre-emphasis
  • Per lane PRBS generator and bit error rate checker
  • Small 12x12mm package

MSH225 LineSpeed Flex 10 Lane Full-Duplex 25G Retimer with RS-FEC

The LineSpeed Flex 10 Lane Full Duplex 25G Retimer with RS-FEC (MSH225) supports up to 10 full duplex lanes (20 channels) with independent rates up to 28 Gbps for high data rate line card applications up to terabits per second. The flexible, multi-protocol SerDes device includes an option for the Clause 91 RS-FEC specified in 802.3bj for 4x25G NRZ interfaces. When the RS-FEC is turned off, the MSH225 device functions as a standard multi-rate and multi-protocol retimer capable of passing data whether encoded or non-encoded. Each lane is independent and supports a broad range of frequencies compatible with 10G, 25G, 40G and 100G Ethernet and OTN standards. With the 100G 802.3bj RS-FEC encode, decode and correction functions enabled, the device will encode data in one direction and decode and correct data (if needed) in the other direction. The IEEE 802.3bj RS-FEC enables additional signal integrity and/or distance capability over copper or optical interconnects and has been specified in multiple standards and MSAs.

The device provides equalization, clock and data recovery, and re-transmitter for up to 20 lanes of serial traffic from 10-15G or 25-28G. It supports multiple on chip error checking and monitoring capabilities, reference clocks and ability to monitor the optional 100G RS-FEC status.

The device is packaged in a small 17x17mm FCCSP for module or daughter card applications. It is pinout and software compatible with the MSH320 100G Gearbox and the MSH322 100G Multi-Link Gearbox.

Application Example:

Key Features:

  • Full duplex 10 lane retimer (20 lanes)
  • Includes 802.3bj Clause 91 RS-FEC (4x25.78G)
  • Support of IEEE and OIF 10, 25, 40 and100G standards for Ethernet and OTN
  • Self-adapting equalizer and eye opening capability
  • Transmitter and TX pre-emphasis
  • Per lane PRBS generator and bit error rate checker
  • Compact 17x17mm package
  • Pin compatible with the MSH320 and MSH322

MSH310 LineSpeed 100G Multi-Mode Gearbox

The LineSpeed 100G Multi-Mode Gearbox (MSH310) is a single chip low power CMOS device designed to support 100G, 40G and 10G standards for line cards or modules supporting next generation data center, enterprise or service provider applications. The device supports 10/11 Gbps serial data up to 25/28 Gbps serial data with minimum external components and includes equalization to support longer reach applications.

The device converts 10 lanes of serial 10/11 Gbps data into 4 lanes of serial 25-28 Gbps data or 10 lanes of 10/11 Gbps data per IEEE 802.3ba and integrates a complete CAUI and OIF-CEI-3.0 transceiver along with a 10:4 or 10:10 multiplexer and 4:10 de-multiplexer.

The MSH310 supports IEEE802.3ba 100G Ethernet plus OIF-CEI-3.0 10G and 25/28G specifications. It supports on-chip PRBS generation and checking.

Application Example:

Key Features:

  • Support of IEEE and OIF 10, 40 and 100G standard
  • Strong self adapting equalizer - eye opening capability
  • CDR & SerDes functions
  • Transmitter and TX pre-emphasis
  • PRBS generator and bit error rate checker
  • Low power standard CMOS

MoSys’ Gearbox supports four modes:

     
    Where:
10G = 9.95G - 11.2G
25G = 24.75G - 28.2G
 


MSH320 LineSpeed Flex 100G Gearbox with RS-FEC

The LineSpeed Flex 100G Gearbox with RS-FEC translates 10G interfaces to 25G interfaces, multiplexing 100G traffic at 10x10G or 10x11.18G to 4x25G or 4x27.95G. The device also supports the IEEE 802.3bj Clause 91 RS-FEC for 4x25G NRZ 100GE interfaces. When configured as a repeater, the device will support up to 10 independent 10G interfaces for Ethernet or OTN. With the 100G 802.3bj RS-FEC encode, decode and correction functions enabled, the device will encode data in one direction and decode and correct data (if needed) in the other direction. The IEEE 802.3bj RS-FEC enables additional signal integrity and/or distance capability over copper or optical interconnects and has been specified in multiple standards and MSAs including SR4, CWDM4 and PSM4.

The MSH320 supports the IEEE802.3ba gearbox function. The electrical interfaces support IEEE and OIF-CEI- 3.0 10G and 25/28G specifications.

Application Example:

Key Features:

  • IEEE 802.3ba Gearbox for Ethernet & OTN
  • IEEE and OIF 10, 40 and 100G electrical standards
  • Supports 802.3bj, Clause 91 RS-FEC Option
    • Specified in CR4, KR4, SR4, CWDM4, PSM4
  • Supports 10x10G independent retimers
  • Self adapting equalizer - eye opening capability
  • Transmitter and TX pre-emphasis
  • Per lane PRBS generator and bit error rate checker
  • Monitor, Alarm and reference clock support

MSH321/322 LineSpeed Flex 100G Multi-Link (MLG) Gearbox

The LineSpeed Flex Multi-Link Gearbox devices (MSH321 for Modules and MSH322 for Line Cards) supports both OIF MLG-1.0 and MLG-2.0 standards that aggregate a combination of 10GE and 40GE links, up to 100G total bandwidth, and converts that to a single 100GE (4x25G) link. The difference between the MLG and a standard gearbox based on IEEE 802.3ba is that rather than requiring all 10 lanes to be bonded as 10x10G with zero ppm offset, MLG allows independent 10GE or 40GE lanes, separated by up to +/- 100ppm to be multiplexed into a single 100GE pipe.

The MoSys MLG devices perform all alignment marker insertion and awareness, idle insertion and deletion, and data alignment required by the OIF MLG standards. As physical interfaces on switching and packet processing ICs move to 25G PHY interfaces for performance and board density, the MLG function allows large scale systems built with these devices to support higher port counts of legacy 10GE and 40GE interfaces.

The devices support IEEE 10G, 40G and 100G interface standards and OIF-CEI-3.0 10G and 25/28G specifications. It supports on-chip PRBS generation and error checking

Application Example:

Key Features:

  • Supports OIF MLG 1.0 and MLG 2.0 Standards
    • 10 Independent 10GE links into 100GE (4x25G)
    • Mix of 10GE and 40GE links into 100GE (4x25G)
  • Supports IEEE and OIF 10, 40, and 100G standards
  • Self adapting equalizer - eye opening capability
  • Transmitter and TX pre-emphasis
  • Per lane PRBS generator and bit error rate checker
  • Monitor, Alarm and reference clock support
  • Small package form factors 12x12mm for module and 17x17 for line cards