MoSys’ Bandwidth Engine Family of ICs is a computational and memory solution with serial interfaces for 100G networking equipment. First generation Bandwidth Engine is optimized for memory access performance, capable of up to 2.7 Giga-accesses per second, up to 24 Gbps throughput, and up to 1.0 Giga-operations per second when utilizing the onboard ALU.
The device architecture relies on three elements:
- A 576Mb multi-banked and multi-partitioned memory array built with high performance, high density 1T-SRAM® memory core.
- Onboard ALUs for the acceleration of common statistics functions in networking applications.
- Sixteen lanes of low latency SerDes, compatible with CEI-11G, supporting full duplex, concurrent operations with a packetized, 90% efficient GigaChip™ Interface transport protocol.
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Bandwidth Engine Products
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Bandwidth Engine Performance
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- Bandwidth Engine provides 8x the density and up to 2x the performance at significantly lower power than traditional QDR SRAM devices.
- Bandwidth Engine has the highest bandwidth capability of any single chip networking memory device.
- Bandwidth Engine is engineered and built for high-reliability carrier class and enterprise applications.
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Technical Support
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MoSys offers a library of technical collateral to assist in the design of your system:
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Product Briefs & White Papers
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Click here to access MoSys documentation
Target Applications
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Bandwidth Engine was engineered to address the quality and reliability requirements of enterprise and carrier class systems. It enables next generation network performance and interconnectedness. Bandwidth Engine is well suited for the following applications:
| Application |
Bandwidth Engine (BE) Advantage |
| Counters & Statistics |
Onboard ALU |
| Traffic Management |
75% read ratio |
| State Memory |
50% read high access rate |
| Queuing & Scheduling |
50% read high access rate |
| Config Tables |
Highest single chip read rate |
| Power Efficient Buffering |
One BE replaces 24 standard memories |
Interoperability Demos
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MoSys has demonstrated interoperability with world class FPGA and ASIC providers. View MoSys Interoperability demonstration videos with Altera, Avago and Xilinx:
MoSys Demonstrates Interoperability with Altera Stratix IV GT FPGA
MoSys Demonstrates Interoperability with Avago Technologies SerDes
MoSys Demonstrates Interoperability with Xilinx Virtex-6 FPGA
Contact MoSys to request a Bandwidth Engine datasheet
Click here for a list of available Bandwidth Engine collateral |
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