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DDR
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DDR3 |
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MoSys’ silicon proven DDR3 support a wide range of data-rates from 800Mbps to 2133Mbps. Chip designers obtain access to risk-free silicon-proven hardened PHY macros at advanced process nodes.
MoSys’ DDR3 PHYs are JEDEC compliant and DFI 2.1 compliant. The PHY is a complete hardened macro requiring no additional IP components. It delivers seamless interoperability with industry standard controllers.
Key Benefits
- Silicon validated designs ensuring lowest risk
- FlipChip ready design supporting 2133 Mbps
- Wirebond ready design supporting 1600 Mbps
- 2.5V or 1.8V IO FET support
- DFI 2.1 Compliant
- Proven interoperability with industry standard memory controllers
Availability
- TSMC 40G
- TSMC 65GP
- Please contact MoSys for all other process variants
Click here for a complete listing of MoSys IP:
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Our Applications
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MoSys in Networking
The explosive demand for internet bandwidth is driving the need for next generation network systems. These systems require significantly more...
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MoSys in Computing
Improved performance and the trend towards multi-core computing is driving the need for next generation high end computing systems...
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MoSys in Consumer/Graphics
MoSys differentiated and patented 1T-SRAM embedded memory IP enables next generation networking SoCs to have 3 times the density in the same...
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MoSys in Storage
The dramatic explosion in information within the enterprise across the extended network in high end storage systems, and the need to have...
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Products 
