MoSys® Bandwidth Engine MSR820 adds on-board intelligence to the burst and access abilities of the MSR622, providing intelligent offload for Counting, Statistics, Metering and Atomic operations. The highly parallel array architecture can be saturated with only 8 SerDes lanes when utilizing the on-board macro functionality. Coupled with the efficient, packetized, serial interface, it enables support of multiple applications within the 576Mbit footprint.


  • 576Mb 1T-SRAM® memory array architecture
    • 3.2 ns core cycle time, < 16 ns read latency
  • Low-latency SerDes technology up to 12.5 Gbps
    • 4, 8 or 16 serial transceivers (TX/RX)
    • OIF CEI-11G-SR and XFI compatible interface
    • Tuned for low-power transmission up to 20 cm
  • High-performance GigaChip® Interface
    • High-efficiency format utilizing scrambling
    • CRC error detection and recovery mechanisms
  • Intelligent Error Management and Bit Safe® Technology
  • High reliability – 1T-SRAM soft error immunity

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