MoSys® Bandwidth Engine family brings fast, intelli- gent memory access to packet processing chipsets. The MSR620 integrates high density memory, a high speed serial interface, 90% efficient transport protocol, and payload burst capabilities to break the access and throughput barriers in networking, storage and video applications.


  • 576Mb 1T-SRAM® memory array architecture
    • 3.2 ns core cycle time, < 16 ns read latency
  • Low-latency SerDes technology up to 12.5 Gbps
    • 4, 8 or 16 serial transceivers (TX/RX)
    • OIF CEI-11G-SR and XFI compatible interface
    • Tuned for low-power transmission up to 20 cm
  • High-performance GigaChip® Interface
    • High-efficiency format utilizing scrambling
    • CRC error detection and recovery mechanisms
  • Intelligent Error Management and Bit Safe® Technology
  • High reliability – 1T-SRAM soft error immunity
  • Advanced debugging capabilities

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