This kit includes an evaluation board for the second generation Bandwidth Engine family in a 19×19 FCBGA package and supports data rates up to 12.5 Gbps.

The FMC Daughtercard is designed to interface to an FPGA development board through the standard, dual FMC configuration such as the Xilinx Virtex-7 VC707 Evaluation Kit. The board can be used stand alone to interface to MoSys Bandwidth Engine 2 devices using SPI or JTAG.

This board has 16 SerDes lanes, eight through each HPC FMC connector, and can be used with all three versions of the Bandwidth Engine 2 family, MSR620 or MSR820.

The board was designed to allow operation using only one of the FMC headers using 8 lanes to the device. When using a single FMC connector the carrier board needs to be checked for mechanical clearance. Carrier boards with a single FMC HPC such as the Altera Stratix V Advanced Systems Development Kit are available from FPGA suppliers as well as 3rd party companies.

Reference material is available upon request to to help you with your design process. To request a Bandwidth Engine FMC Daughtercard or get the latest update and access to the information available, please

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