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Publication Date Title
Embedded October 24, 2014 Achieving 200-400GE network buffer speeds with a serial-memory coprocessor architecture
October 24, 2014 - Embedded
Achieving 200-400GE network buffer speeds with a serial-memory coprocessor architecture
Linley Tech Processor Conference 2014 October 22, 2014 Trade-Offs of a Coprocessing Engine vs. Fixed-Memory TCAM
October 22, 2014 - Linley Tech Processor Conference 2014
Trade-Offs of a Coprocessing Engine vs. Fixed-Memory TCAM
MoSys, Inc. October 15, 2014 Memories for Extreme Networking, MemCon 2014
October 15, 2014 - MoSys, Inc.
Memories for Extreme Networking, MemCon 2014
GigOptix September 17, 2014 GigOptix to Showcase 100Gbps Live Demos With Partners at ECOC 2014
September 17, 2014 - GigOptix
GigOptix to Showcase 100Gbps Live Demos With Partners at ECOC 2014
EDN July 25, 2014 Deliver at 100G: The impact of smart memory
July 25, 2014 - EDN
Deliver at 100G: The impact of smart memory
Xcell Journal by Xilinx, Inc. July 15, 2014 Goodbye DDR, Hello Serial Memory
July 15, 2014 - Xcell Journal by Xilinx, Inc.
Goodbye DDR, Hello Serial Memory
VLSI Circuits Symposium 2014 June 12, 2014 Early Detection and Repair of VRT and Aging DRAM Bits by Margined in-field BIST
June 12, 2014 - VLSI Circuits Symposium 2014
Early Detection and Repair of VRT and Aging DRAM Bits by Margined in-field BIST
Info:

Abstract: Studies on DRAMs in high performance computing clusters and servers have concluded that memory errors in the field are dominated by hard faults, which cannot be fixed by scrubbing. Our accelerated life testing of embedded DRAM products shows that bits can degrade gradually. We propose improving system availability by performing in-field repair at the chip level. One page at a time, user data is copied to a temporary page and the page is stress tested with a long effective refresh time. Degrading memory cells are detected and repaired before any errors occur. Our 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology with 8 metal layers achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.

Conference proceedings to be available soon at IEEE Xplore.

Linley Tech Carrier Conference 2014 June 11, 2014 100G+ Adaptive PHY Technology for Scalable Reach and Design Flexibility
June 11, 2014 - Linley Tech Carrier Conference 2014
100G+ Adaptive PHY Technology for Scalable Reach and Design Flexibility
Info:

Author:

John Monson, VP of Marketing & Sales

Abstract:

For next-generation platforms and high-density line cards to extend into the Terabit per second range, low power, high-speed 25G+ PHYs, high-density connections at the faceplate, and flexibility of device placement will be required. In order to meet these requirements, 25G+ CDR and PHY devices must support a wide variety of rates and configurations, flexible distances, and broad electrical standards and improve ease-of-use. In this talk, MoSys will introduce its latest LineSpeed PHY technology and describe application trends, timelines and trade-offs for future platforms.

Day 2, Session 5: Pervasive 100G Interconnects presentation by MoSys is available by request from The Linley Group.

eASIC May 13, 2014 eASIC Announces Support for GigaChip Interface
May 13, 2014 - eASIC
eASIC Announces Support for GigaChip Interface
EDN May 05, 2014 Improve 400 GbE and 100 GbE performance
May 05, 2014 - EDN
Improve 400 GbE and 100 GbE performance
EE Times May 05, 2014 Serial-Interface Memory Architectures for 100 GbE
May 05, 2014 - EE Times
Serial-Interface Memory Architectures for 100 GbE
EE Times April 14, 2014 Scaling the 100 GbE Memory Wall
April 14, 2014 - EE Times
Scaling the 100 GbE Memory Wall
Xcell Daily Blog by Steve Liebson, Xilinx March 13, 2014 MoSys Bandwidth Engine 2 adds Go-Juice to Kintex UltraScale FPGA via multiple 15.625Gbps lanes
March 13, 2014 - Xcell Daily Blog by Steve Liebson, Xilinx
MoSys Bandwidth Engine 2 adds Go-Juice to Kintex UltraScale FPGA via multiple 15.625Gbps lanes
Xcell Daily Blog by Steve Liebson, Xilinx March 11, 2014 MoSys Bandwidth Engine 2 and Xilinx Kintex UltraScale FPGA have a 15.625Gbps conversation at OFC
March 11, 2014 - Xcell Daily Blog by Steve Liebson, Xilinx
MoSys Bandwidth Engine 2 and Xilinx Kintex UltraScale FPGA have a 15.625Gbps conversation at OFC
Linley Group Networking Report February 10, 2014 MoSys Memory Adds Search
February 10, 2014 - Linley Group Networking Report
MoSys Memory Adds Search
Info:

"When moving beyond 400Gbps throughputs, network-processor (NPU) designers face a pin-count crisis. Those same engineers worked hard to minimize cost and power by using traditional DRAM wherever possible, but that strategy is unsustainable. As a result, serial memories are coming to next-generation routers. Broadcom (then NetLogic) led this trend with search coprocessors that use Interlaken Look-Aside interfaces (see MPR 12/17/12, “Broadcom’s NLA12000 Leaps Forward”). This quarter, MoSys will start production of its Bandwidth Engine 2 (BE-2) family (see NWR 3/11/13, “MoSys Cranks Up 400Gbps Line Cards”), which offers a serial alternative to specialty memories such as QDR SRAM and RLDRAM/LLDRAM."

The full article is available with subscription access to the Linley Group Networking Report website.

Xcell Daily Blog by Steve Liebson, Xilinx February 05, 2014 3rd-Generation Bandwidth Engine from MoSys needs sixteen 28Gbps lanes to strut its stuff
February 05, 2014 - Xcell Daily Blog by Steve Liebson, Xilinx
3rd-Generation Bandwidth Engine from MoSys needs sixteen 28Gbps lanes to strut its stuff
Linley Tech Data Center Conference 2014 February 05, 2014 Intelligent Offload Supporting Data Center Equipment at 100G+
February 05, 2014 - Linley Tech Data Center Conference 2014
Intelligent Offload Supporting Data Center Equipment at 100G+
Info:

Author:

Michael Miller, VP of Technology Innovation & System Applications

Abstract:

MoSys reveals the third generation architecture of the Bandwidth Engine IC which delivers the high performance necessary for advanced Datacenter Networks. Firewall appliances have grown from single processor boxes to clusters of compute, route and inspection nodes which perform sophisticated security detection and prevention measures. Inside the datacenter the distributed nature of cloud content drives a many-fold times higher East-West bandwidth. Both applications are critically important to delivering a robust, low latency and high bandwidth user experience.

The Day 1, Session 3: Advancements in Packet Processing presentation by MoSys is available by request from The Linley Group.

Xcell Daily Blog by Steve Liebson, Xilinx January 29, 2014 MoSys Bandwidth Engine 2 cozies up to Virtex-7 FPGA using 16 SerDes transceivers running at 14.07GHz
January 29, 2014 - Xcell Daily Blog by Steve Liebson, Xilinx
MoSys Bandwidth Engine 2 cozies up to Virtex-7 FPGA using 16 SerDes transceivers running at 14.07GHz
EDN January 14, 2014 How to overcome memory-imposed access rates and bandwidth constraints
January 14, 2014 - EDN
How to overcome memory-imposed access rates and bandwidth constraints
EDN December 02, 2013 Serialized Memory Interface Gains Momentum
December 02, 2013 - EDN
Serialized Memory Interface Gains Momentum
Gazettabyte September 25, 2013 OIF demonstrates its 25 Gig interfaces are ready for use
September 25, 2013 - Gazettabyte
OIF demonstrates its 25 Gig interfaces are ready for use
Optical Internetworking Forum September 24, 2013 Multi-Vendor Interoperability Testing of CFP2, CPAK and QSFP28 with CEI-28GVSR and CEI-25G-LR Interface
September 24, 2013 - Optical Internetworking Forum
Multi-Vendor Interoperability Testing of CFP2, CPAK and QSFP28 with CEI-28GVSR and CEI-25G-LR Interface
Optical Internetworking Forum September 11, 2013 OIF To Showcase Record Number of Interoperability Demonstrations at ECOC 2013
September 11, 2013 - Optical Internetworking Forum
OIF To Showcase Record Number of Interoperability Demonstrations at ECOC 2013
Info:

See MoSys technology at this year's OIF Interoperability demos at ECOC 2013.

Particpants include: Amphenol, Applied Micro, Cisco, Finisar, Fujitsu Optical Components, Inphi, Molex, MoSys, Semtech, TE Connectivity, and Xilinx.

Technologies demonstrated during the testing include host ICs with VSR SerDes capability, host PCB traces, optical module connectors, high-speed electrical I/O and backplane connectors, module retimers, heat sinks and optical transceivers all operating with 28G electrical interfaces. Agilent Technologies Inc. and Tektronix, Inc. will supply test equipment used in the demonstration.

Click here for the full press release.

Hot Chips 25 August 26, 2013 Second Generation Bandwidth Engine? IC Breaks 4.5 Billion Accesses/sec
August 26, 2013 - Hot Chips 25
Second Generation Bandwidth Engine? IC Breaks 4.5 Billion Accesses/sec
Linley Tech Carrier Conference 2013 June 12, 2013 Evolving Toward 1Tbps Line Cards
June 12, 2013 - Linley Tech Carrier Conference 2013
Evolving Toward 1Tbps Line Cards
Info:

Author:

Michael Miller, VP of Technology Innovation & System Applications

Abstract:

As designers develop 400Gbps line cards and consider 1Tbps designs, serial interfaces will play dominant roles. At 400G, the traditional packet processing models are broken. High-performance-serial networking memories, gearboxes, and nx25G retimers will emerge to address 1Tbps ecosystem requirements. Pin I/O efficiency, reach and functionality are critical to deliver performance and manage interconnect, package and power limitations. This presentation will explore line-card architecture from a serial-interface devices (datapath & look-aside) perspective and the ramifications as they evolve towards 1Tbps. 

The Day 1, Session 3: High-Performance Data Planes presentation by MoSys is available by request from The Linley Group.

IEEE Micro June 01, 2013 An Intelligent RAM with Serial I/Os
June 01, 2013 - IEEE Micro
An Intelligent RAM with Serial I/Os
Info:

Abstract: 

Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine® family of ICs provides a significant improvement in effective memory performance by using high-speed serial I/Os, many banks of memory, a low-latency, highly efficient protocol, and intelligence within the device. The first member of the family can perform 2 billion 72-bit reads per second or 1 billion read-modify-write operations per second.

The full paper is available to IEEE Xplore subscribers or for purchase via IEEE Micro.

Linley Group Networking Report April 08, 2013 MoSys Gears Up for PHYs
April 08, 2013 - Linley Group Networking Report
MoSys Gears Up for PHYs
Info:

 "At last month’s OFC, MoSys announced a 100Gbps gearbox PHY for data centers and networking applications. The MSH310 gearbox multiplexes and maps 10 lanes running at 10Gbps to 4 lanes running at 25Gbps. Per the standard requirements, it de-skews signals across the 10 lanes, adjusting for different propagation delays to enable 100G Ethernet and to simplify board layout. The chip also performs demultiplexing functions from 4x25Gbps to 10x10Gbps."

The full article is available with subscription access to the Linley Group Networking Report website.

Linley Group Networking Report March 11, 2013 MoSys Cranks Up 400Gbps Line Cards
March 11, 2013 - Linley Group Networking Report
MoSys Cranks Up 400Gbps Line Cards
Info:

"Mushrooming Internet traffic is giving rise to greater density line cards where the bandwidth between an NPU/ASIC or FPGA and memory is becoming a bottleneck. Directly addressing this issue, the 15Gbps GCI from MoSys is the fastest interface available for networking designs. In a 100GbE packet time, the BE-2 can perform eight operations, which could be used to read memory, write memory, update statistics, perform metering, and read tables. This new device is an attractive solution for high-capacity line cards alongside a Xilinx or Altera FPGA, which supports GCI."

The full article is available with subscription access to the Linley Group Networking Report website.

Engineering TV January 29, 2013 MoSys Bandwidth Engine Helps Out 10G Networking - DesignCon 2013
January 29, 2013 - Engineering TV
MoSys Bandwidth Engine Helps Out 10G Networking - DesignCon 2013
Linley Group Microprocessor Report November 12, 2012 Networking Spurs Memory Evolution
November 12, 2012 - Linley Group Microprocessor Report
Networking Spurs Memory Evolution
Info:

"In 1975, people were queuing up to buy Pong, four-function calculators cost $40, and RAM was faster than microprocessors. Technology has changed for the better since then—except for the relative performance of memory and processors. Memory is now s-l-o-w, and this is a problem. Computers can hide behind caches, but high-performance real-time systems can’t. At the recent Linley Tech Processor Conference, GSI, Micron, and MoSys presented various solutions for improving memory technology. All three have memories for designers of high-speed networking systems who are willing to pay more per bit to achieve greater performance and advanced functions while avoiding the hidden cost of commodity DRAM."

The full article is available with subscription access at the Linley Group Microprocessor Report website.

EE Times November 01, 2012 Networking Memories: Intelligence for 400G App Acceleration and Host Offload
November 01, 2012 - EE Times
Networking Memories: Intelligence for 400G App Acceleration and Host Offload
EE Times September 06, 2012 Networking Memories - High Access Rates for Packet-header Processing
September 06, 2012 - EE Times
Networking Memories - High Access Rates for Packet-header Processing
EE Times August 31, 2012 Networking Memories for Buffering Applications
August 31, 2012 - EE Times
Networking Memories for Buffering Applications
EE Times April 20, 2012 MoSys combines design, process and test to break the 2 billion accesses per second barrier
April 20, 2012 - EE Times
MoSys combines design, process and test to break the 2 billion accesses per second barrier
EE Times November 01, 2011 Overcoming 40G/100G SerDes design and implementation challenges
November 01, 2011 - EE Times
Overcoming 40G/100G SerDes design and implementation challenges
Hot Chips 23 August 22, 2011 Bandwidth Engine? Serial Memory Chip Breaks 2 Billion Accesses/sec
August 22, 2011 - Hot Chips 23
Bandwidth Engine? Serial Memory Chip Breaks 2 Billion Accesses/sec
EE Times June 02, 2011 Beat the top 3 limiting constraints in 100G designs
June 02, 2011 - EE Times
Beat the top 3 limiting constraints in 100G designs
Electronic Design February 17, 2011 Stratix IV FPGAs First To Support GigaChip Interface
February 17, 2011 - Electronic Design
Stratix IV FPGAs First To Support GigaChip Interface
Embedded October 13, 2010 A Bumpy Road to High-Speed Networking
October 13, 2010 - Embedded
A Bumpy Road to High-Speed Networking
Silicon Cowboy June 15, 2010 MoSys Fires Up the Bandwidth Engine
June 15, 2010 - Silicon Cowboy
MoSys Fires Up the Bandwidth Engine
Heavy Reading February 02, 2010 Router Memory Gets a 100G Makeover
February 02, 2010 - Heavy Reading
Router Memory Gets a 100G Makeover
EE Times February 02, 2010 MoSys tips memory chips in new silicon drive
February 02, 2010 - EE Times
MoSys tips memory chips in new silicon drive
 
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