We are currently seeking a Global Circuit Designer to be responsible for various top level and digital circuit implementations. These include items such as global power and clock distribution, customized logic gate implementation, I/O integration, and ESD. In addition, the GCD will be the primary interface between the integration team and the various internal and external library developers for timing, power, and clock interface issues.
This person will be responsible for the implementation of embedded SRAM and Register Files for the next generation Bandwidth Engine. Will interface with logic/architecture, physical design and layout teams; and implement high speed, low power and area efficient embedded SRAM and Register File macros for multi-core processor engines.
Design/implement custom high performance, low power and area efficient memory macros; SRAMs, Dual-Ports and Multi-Ports Register Files according to logic/architecture teams spec.
Perform floor planning and layout guidance/supervision.
Work closely with physical design/integration team for seamless chip level integration.
Circuit simulation, layout extraction, timing /power characterization and timing model generation.
Implement robust circuit technique to ensure high quality and high yielding silicon.
Perform noise, EM/IR analysis and macro functional verification.
BS. in Electrical Engineering, MSEE preferred.
5+ years of related experience which involve robust dynamic circuit design implementation.
Experience with high performance low power circuit design techniques.
Experience with Cadence and Synopsys Circuit and layout tools.
Prior hands-on design experience with SRAMs or Register File based macros required.
Basic programming skills (preferably Python or Perl) for design optimization and verification
The Firmware/Software engineer will be responsible for developing firmware and software package for driving FPGA-based silicon validating system for MoSys Serdes and Memory products. He/She will work with application groups to develop and maintain codes ranging from low-level drivers to high level GUI for customer demo boards and system applications. This person will also develop a flow-based GUI for in-house tester to achieve maximum engineering and manufacturing efficiency.
Develop serial communication drivers for USB to SPI, I2C, JTAG and MDIO.
Develop GUI on Linux/Windows for customers to evaluate MoSys Serdes/Memory products.
Create GUI to execute flow based test software to facilitate silicon bring up and data collection.
Create a software platform to bridge the gap between pre-silicon verification and post-silicon validation.
Create C compiler to support internal and external customers to program MoSys next generation Bandwidth Engine products.
Develop/maintain software for lab instrument automation and test hardware control.
MSEE with 2 years or BSEE with 4 years of related work experience.
Proven skills in C/C++ programming and familiar with object-oriented programming methodology.
Demonstrated GUI design experiences.
Familiar with assembly language is desired. Familiar with Lex and Yacc (Flex and Bison) is a plus.
Familiar with Python. Knowledge of other scripting languages is a plus.
Understand SPI, I2C, JTAG, GPIB and MDIO protocol and low level drivers.
Knowledge of hardware, digital design and design verification is desired.
Experience with FPGA and Xilinx or Altera design tools is a plus.
MoSys is seeking an entry-level analog and mixed-signal verification engineer to be a part of our high-speed SerDes development team. This position involves the design and verification of high-speed SerDes circuits for our Bandwidth Engine® and LineSpeed™ products.
Analog and mixed-signal design and verification of circuits used in high-speed physical layer transceivers (SerDes)
Verification of circuits and system against design specifications and product requirements
Simulating and designing analog circuits using Spice simulators.
Matlab modeling and simulation of CDR loops.
Creating mixed signal Verilog/AMS models of SerDes and simulating them.
BSEE and 3+ years experience, or MSEE
Fundamental understanding of circuit theory, design, and layout in advanced CMOS process technologies (65nm and below)
Experience with the Cadence IC design environment and spice simulators.
Ability to work effectively in a team environment, good documentation of verification results and good communication skills.
Understanding of PLLs, CDRs, transceivers, equalizers, SerDes architecture and implementation is a plus.
Experience with modeling and simulation in matlab, using mixed-signal simulators like verilog-ams is a plus.
Knowledge of digital design and verilog is a plus
Hands on experience in high speed SERDES testing and characterization is a plus
This candidate will automate, develop, deply, support and own CAD and integration tools and flows that enhance the efficiency and productivity of the MoSys design teams. The candidate will work/communicate directly with multiple foundry PDKs for leading edge processes. This candidate should be able to develop, deploy and own in-house solutions for any design issues encountered.
Support the current tools and flows in place
Develop new solutions as needed
Support EM/IR solutions at MoSys
Support Cadence/DM solutions
BSEE or MSEE with an electrical or computer background
5-8 years of experience in design automation / CAD
Hands-on experience with Cadence tools (Virtuoso/Composer/Layout)
Experience with version control/config management and release methodologies
Strong coding experience on PERL, TCL and SKILL languages
Hands-on experience in EM/IR tools at the custom and ASIC level
This position is on the Bandwidth Engine design team. The Bandwidth Engine products from MoSys, Inc. are memory dominated devices with ALUs and low-latency, high-bandwidth SerDes interfaces. This family of ICs is optimized for high-bandwidth, high-access-rate applications such as networking, storage and video.
This person will work on the logic design of the Bandwidth Engine SoC. He/She will develop and implement microarchitectures of various features on the next generation high-speed serial memory chip. Excellent logic design skills and experience with developing RTL that meets functionality, timing and power constraints is needed. Background in processor logic design or complex ASICs is required, with excellent knowledge of Verilog and synthesis tools.
BS or MS in EE and 5 years of relevant industry experience
Excellent experience with development and implementation of complex microarchitecures and RTL design.
Experience in Verilog and PERL
Experience in synthesis tools like Design Compiler
Excellent team player, innovative and self-driven with good communication skills including documentation.
MoSys is currently seeking a self-motivated hands-on validation engineer. This person will lead the validation of high-speed (up to 28 Gbps) PHY ICs. We are looking for a star performer that is able to take on a growing number of new products at MoSys.
BS degree plus at least 5 years’ experience with mixed-signal IC validation
Strong background in software and software control of lab equipment (C++, Perl, Python, CVI / LabWindows etc.)
Hands on experience with multi-lane multi-standard SERDES testing, measurement of the key performance parameters and the ability to define, develop and execute both test platforms and validation plans for new products.
Preferably skilled in high speed (>10 Gbps) signal integrity measurements and de-embedding techniques
Experience in test / data acquisition automation and concise presentation of measurement results. Ability to summarize the observed data and recommend plan of actions.
Detailed, working knowledge of lab equipment (Oscilloscopes, Function Generators, Spectrum Analyzers, BERTs, etc, automated control of equipment using the GPIB/488 bus ) and lab validation techniques
Experience in Unix/Linux/Windows environment and shell scripting
Validation plan, schedule, dependencies and test setup development skills
Good system level debugging / troubleshooting skills
Test board and interface design skills
Effective communication and presentation skills
Ability to work within an international, cross functional team.
Ability to prepare for and perform post-silicon validation
Click here to apply for the Staff Engineer, Validation, Post Silicon (Santa Clara, CA) position!
MoSys is seeking a Sr. Analog Circuit Design Engineer to be responsible for the design and implementation of memory IP voltage regulator and charge pump for next generation Bandwidth Engine products. Will interface with product/test, physical design and layout teams; to implement low power and area/power efficient voltage regulators used in the embedded DRAM macro.
Design/implement low power and high efficiency internal voltage generator & charge pump circuit design for memory eDRAM
Perform circuit modeling, AC/DC/Transient simulation, characterization, and documentation
Perform layout guidance/supervision, layout extraction and post layout simulation
Perform noise, EM/IR analysis
Work closely with product engineers for optimum product bring-up and silicon debug
BS in Electrical Engineering, MS preferred plus 3-5 years experience
Solid understanding of transistor/device operation
Hands on BGR/Comparator/Charge-pump design experience required
Experience with Cadence and Synopsys Circuit and layout tools
Prior experience with embedded DRAM (or familiar w/ DRAM operation) preferred
Basic programming skills (preferably Python or Perl) for design optimization and verification
MoSys offers 6 month internship positions for engineering students at the graduate levels, and provides an exciting, real-world opportunity to gain valuable, hands-on experience, giving you the chance to put your education into action.
MoSys interns are not brought on to perform side projects or mundane tasks. Rather, our interns participate in critical, high-profile projects that directly shape MoSys as an evolving and innovative company. If you are up for a challenge, an internship with MoSys may be what you are looking for.
Interns are considered valuable members of the MoSys team and therefore may earn many of the benefits available to full-time employees, including:
Real-world experience with leading-edge technologies
Networking with and mentoring by experienced MoSys managers and team members
Consideration for full-time employment when you graduate based on internship performance
Intern Positions are available in one or more of the following fields:
High speed circuit design and verification
Logic design and verification
FPGA implementation and bringup
Parallel tester software development
Memory and SerDes characterization
ESD and latchup analysis
Design for Test implementation
PCB board design for test and characterization
Signal and Power Integrity analysis for 10-28 Gbps serial links
MoSys is looking for fast learners who are currently enrolled in Master's, or doctorate programs in the field of Electrical Engineering. Candidates should have a grade point average of 3.5 or higher on a 4.0 scale. An ideal candidate will also possess exceptional written and spoken communication skills, excellent interpersonal skills, previous internship or work experience, proven leadership skills and a positive attitude toward working on and building teams. Versatility and the flexibility to adapt to new situations are essential.
The MoSys Engineering Rotation Program offers select graduates the opportunity to work closely with our talented engineers on critical projects and have an immediate impact in the company.
The MoSys Engineering Rotation Program is a full-time 12-month technical development program. The Engineering Rotation Program gives participants an opportunity to experience several different rotational assignments before assuming a full-time regular position in the company. Engineers in the program complete three assignments during four month long high-profile placements across the corporation. Each assignment is challenging, designed to provide the Engineer with a unique experience and contributes to the company’s goals and objectives.
Final employment placement is determined by candidate interest as well as company need.
PhD or MS in Electrical Engineering
Strong technical knowledge and an ability to adapt quickly to new projects
Excellent written/verbal communication skills and the ability to work well in a team environment
MoSys is seeking a Senior Logic Design Engineer, to be a part of our LineSpeed™ product team. This position involves the architecting, RTL design, and implementation of high-speed, physical layer transceiver (PHY) solutions.
Architecture and RTL design of high-speed PHY (SerDes) standard IC products
Work closely with integration and design verification teams to meet functional, timing, and power constraints
BS or MS in CS or EE and 10+ years of relevant industry experience
Background in Ethernet Physical Layer logic design or similar is required, with excellent knowledge of Verilog and synthesis tools.
Experience in development of 10G, 40G, and 100G Ethernet physical layer solutions
Experience with Verilog, scripting, revision control, LINT, etc.
Experience with synthesis tools (such as Design Compiler), timing constraints, and timing analysis tools
Excellent team player, innovative and self-driven with good communication skills, including documentation.
We are looking for a talented Integration Layout Engineer for developing physical layout of high speed analog integrated circuits and developing integration scripts. This person will be expected to work independently with minimum guidance and also use innovative approaches when drawing layout and writing scripts. Should be able to maintain the project schedules while being proficient in understanding the complexities involved in high speed analog layout design and writing CAD/integration scripts. Should also have a strong desire to learn and explore new technologies while demonstrating good analysis and problem solving skills. Prior knowledge and experience in CAD tool usage and Scripting is a must; specifically, Cadence, Synopsys and Mentor tools. Scripting knowledge on Perl, Skill and Tcl is must.
The Integration Layout Engineer will be responsible for physical design of high frequency circuits in a fast paced environment and developing integration/CAD scripts. Minimum expectations include:
Delivering high quality layout that conforms to all design requirements in advanced technologies.
Developing integration and CAD scripts
Understanding the constraints of Floor Plan, hierarchical planning (top down and bottom up) and layout integration
Strong communication with various design teams to ensure strong understanding of circuit requirements of layout and scripting
Meeting project milestone deadlines
Full self-sufficiency in debugging / troubleshooting complex physical design verification issues
B.Tech (ECE) or above with 2-4 years of analog/mixed signal layout design and CAD
Able to write scripts in Perl, Tcl and Skill languages
Custom layout experience, must include high frequency
In-depth knowledge on parasitic effects, proximity effects & nanometer challenges and scripting
Full familiarity with Cadence, Synopsys and Mentor Graphics tools
Must have experience in lower design processes (28nm, 45nm, 65nm).
Outstanding written and verbal communication
Good team player, self motivated and excellent time management skills
The Analog Layout Engineer will work on design for SerDes which works at 25Gbps and above in next generation MoSys product series. The team provides a complete solution for various activities like layout issues on 28nm, 45nm & 65nm techology nodes and support to reach the next level with high confidence.
Analog layout from block level to Chip level.
Strong communication in between various design teams to ensure strong understanding of circuit requirements of layout.
Good Knowledge in basics characteristics of electronic components such as transistor, resistor, capacitor, diode and bipolar.
Good understanding of fabrication process.
Familiar with layout techniques and issues in 28nm, 45nm & 65nm Technology nodes.
Understanding of layout impact on device matching, noise coupling, deep sub micron effects.
Understand the importance of signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
Should have good debugging skills in all physical verification checks like LVS,DRC,DFM and Antenna.
Good knowledge on EMIR analysis and ESD path checks.
Thorough working knowledge in physical design and verification tools - Cadence tools (Virtuoso-L,Virtuoso-XL and Schematic composer), Mentor Graphics Calibre and Apache EMIR Analysis.
Knowledge of scripting languages such as Perl and Skill is a plus.
Good verbal/written communication skills with local and remote teams