Key Duties/Responsibilities

As a system validation engineer, you will be responsible for validating MoSys revolutionary Bandwidth
Engine products, debug/diagnosis of system performance and ensure interoperability between custom
ASIC and FPGA. You will develop/maintain FPGA based test bench to debug and characterize high speed SerDes and high speed memory in our Bandwidth Engine products.

Responsibilities

• Develop/maintain FPGA based test bench.
• Debug/Diagnosis Bandwidth Engine products on FPGA platform.
• Deliver customer samples validated by system test.
• Characterize product system performance according to datasheet.
• Work with design and product groups to resolve design and product test issues.

Requirements

• MSEE with 3 years or BSEE with 5 years of related work experience.
• Solid RTL design background. Familiar with verilog simulation and waveform debug tool.
• Experience in using Altera or Xilinx design tools.
• Familiar with high speed SerDes and communication protocol is a plus.
• Skills in TCL, Perl, or other scripting language are desired.
• Self-starter and work well in a team environment.

MoSys internship opportunities include engineering positions at the undergraduate and graduate levels. They provide you the opportunity to gain valuable, hands-on experience, giving you the chance to put your education into action.

MoSys internships are designed to benefit you and MoSys. MoSys interns are not brought on to perform side projects or mundane tasks. Rather, our interns participate in critical, high-profile projects that directly shape MoSys as an evolving and innovative company.

If you are up for a challenge, an internship with MoSys may be what you are looking for.

The Benefits

Interns are considered valuable members of the MoSys team and therefore may earn many of the benefits available to full-time employees, including:

• Real-world experience with leading-edge technologies
• Competitive salaries
• Networking with and mentoring by experienced MoSys managers and team members
• Consideration for full-time employment when you graduate based on internship performance

How to Qualify

MoSys is looking for fast learners who are currently enrolled in Bachelor's, Master's, or doctorate programs in engineering, science, and business-related fields. Candidates should have a grade point average of 3.0 or higher on a 4.0 scale. An ideal candidate will also possess exceptional written and spoken communication skills, excellent interpersonal skills, previous internship or work experience, proven leadership skills and a positive attitude toward working on and building teams. Versatility and the flexibility to adapt to new situations are essential.

2012 Intern Positions are available in one or more of the following fields:

• High speed circuit design and verification
• Logic design and verification
• FPGA implementation and bringup
• Lab automation
• Parallel tester software development
• Memory and SerDes characterization
• ESD and latchup analysis
• Design for Test implementation
• PCB board design for test and characterization

MoSys, Inc. in Santa Clara, CA has a Signal Integrity Engineer position to define signaling and package technology for high performance.  Analyze and generate power delivery network requirements.  Advise on Signal Integrity and solve signal and power integrity problems for semiconductor intellectual property customers.  Analyze cost, Signal Integrity, Design for Manufacturability and drive to a high-volume package design.  Design and conduct detailed testing and measurements.  Master of Science degree in Electrical or Electronics Engineering and two years of experience in design and analysis of high performance signal and power integrity in package and printed circuit board design or a Bachelor of Science degree in Electrical or Electronics Engineering and five years of above experience.  Experience with electromagnetic field-solvers, time / frequency domain analysis, high speed SerDes, high-performance Input / Output technologies and in correlating simulation results with lab measurements using oscilloscopes, Time Domain Reflectometry's, Vector Network Analyzer's and spectrum analyzers.

Send resumes to Tammy Carr at 3301 Olcott Street, Santa Clara, CA 95054.

This position is on the Bandwidth Engine design team. The Bandwidth Engine products from MoSys, Inc. are memory dominated devices with ALUs and low-latency, high-bandwidth SerDes interfaces. This family of ICs is optimized for high-bandwidth, high-access-rate applications such as networking, storage and video. The Bandwidth Engine IC includes 576 Mb of memory and a 10G SerDes I/O.

Responsibilities

• Place and Route at block level and chip level
• Custom Clock Tree / Clock Tree Synthesis (CTS) at block level and chip level
• Integration of Custom and ASIC blocks
• Work closely with CAD, Synthesis, STA and Physical verification teams for a successful project

Requirements

• MSEE with 10 years experience or BSEE with 12 years experience
• Experience in Physical Design of 65nm and 45nm technologies using Cadence Tools
• Experience in multimillion gate deisgns from netlist to GDS on more than 5 advanced node full chip (flip chip) designs
• Experience in hierarchical P&R
• Expert user of Cadence SOC Encounter - Floor-Planning, Place & Route and Clock Tree Synthesis
• Strong debugging skills including STA, CTS and Physical verification
• Good experience with Celtic - Signal Integrity and Crosstalk analysis
• Must be an expert user of TCL, SOC Encounter DB and Perl/Python scripting
• Hands-on experience on Cadence Virtuoso
• Good interaction across CAD, Synthesis, STA and Physical verification teams
• Layout experience will be added advantage

Description

As a senior/staff DFT engineer, you will be responsible for the architecture and design implementation of DFT features in MoSys revolutionary Bandwidth Engine products. You will deliver cutting edge test solutions to production.

Responsibilities

• Design, implementation, and verification of AC/DC scan, JTAG, memory BIST, logic BIST.
• Simulation and verification of DFT design.
• Scan compression and ATPG.
• Fault modeling and test coverage analysis.
• Post silicon validation in both lab and ATE environments.

Requirements

• MSEE with 5 years or BSEE with 7 years of related work experience.
• Hands-on experience with Testkompress, BSDArchitect, DFT compiler.
• Familiar with verilog simulation and waveform debug tool.
• Experience with AC/DC scan ATPG, boundary scan and SDF-annotated pattern simulation.
• Ability to perform fault/test coverage analysis and improvement.
• Experience with post silicon validation. Ability of ATE debug is a big plus.
• Skills in C/C++, TCL, Perl, Python are desired. Familiar with assembly is a plus.
• Self-starter and work well in a team environment.

Responsibilities

• Design and verification of multi protocol high speed serdes IO.
• Define the serdes micro-architecture , design digital blocks such as clock and data recovery, adaptation logic which interface with the analog functionality of the serdes.  Colloborate with chip architect and analog designers to specify, design, synthesize, simulate  & verify  these digital blocks.
• Work with verification engineer on switch level and mixed mode verification of the full serdes including digital and analog blocks.

Requirements

• MSEE with 4 years or BSEE with 6 years of work related experience.
• Thorough understanding of serdes architectures, clock and data recovery designs and trade-offs.
• Proficient in verilog, rtl, verilog modeling and digital verification.
• Knowledge of switch level and mixed mode simulation of mixed signal designs.
• Knowledge of transistor level behavior of circuits and tools used in their design.
• Knowledge of scripting and automation  with shell, perl, tcl and python.

Responsibilities

• Develop high speed SerDes architectures, design of new SerDes from initial concept and specification through final verification and conformance to customer requirements.
• Model and simulate various architectures using MatLab or other higher language/ tools.
• Interface with marketing and digital architects to evaluate various features.
• Interface with and guide individual circuit blocks by providing typical and max/min specs.
• Evaluate design performance with actual circuit performances folded back into system model.
• Characterize circuit blocks and fold imperfections back into system model.

Candidate's background should include extensive experience in SerDes architecture development, participation in SerDes standards committees, working knowledge of a set of common SerDes standards and electrical requirements, and extensive knowledge in SerDes applications.

Requirements

• BSEE, MSEE and PHD preferred, with a minimum 10 years experience in high-speed SerDes design and architecture development.
• Proficiency in using software tools for SerDes system development and circuit simulation
• Experience in SerDes development at >10Gbps, Experience at >25Gbps is a plus
• Excellent verbal and written communication skills is a must
• Understanding of analog circuit design is a plus
• Should be willing to work independently as well as in teams

Description

This candidate will automate, develop, deply, support and own CAD and integration tools and flows that enhance the efficiency and productivity of the MoSys design teams. The candidate will work/communicate directly with multiple foundry PDKs for leading edge processes. This candidate should be able to develop, deploy and own in-house solutions for any design issues encountered.

Responsibilities

• Support the current tools and flows in place
• Develop new solutions as needed
• Support EM/IR solutions at MoSys
• Support CircuitERC
• Support Cadence/DM solutions

Requirements

• BSEE or MSEE with an electrical or computer background
• 5-8 years of experience in design automation / CAD
• Hands-on experience with Cadence tools (Virtuoso/Composer/Layout)
• Experience with version control/config management and release methodologies
• Strong coding experience on PERL, TCL and SKILL languages
• Hands-on experience in EM/IR tools at the custom and ASIC level
• Expertise with Linux and Shell scripting 

Description

• Ability to analyze and synthesize problems and propose solutions.
• Prior ASIC/FPGA customer experience is preferred
• Create verification plans at module and chip level for complex SOC's
• Develop a test bench at module and chip levels using verification platforms and tools based on Verilog, SystemVerilog, and C
• Develop efficient system/chip level test and regression environments using scripting languages
• Generate the test cases and run simulations to achieve code and functional coverage goals
• Engage with design team to communicate and fix the bugs field during the verification.
• Help debug FPGA issues on the hardware platform

Technical Skills

• Must be a hands-on Verification engineer in an ASIC/FPGA environment with LAN, SAN and chip interconnect background.
• Good coding and documentation skills
• Must be conversant with system level verification
• Ability to design environments for scalability and reuse with verification and validation goals in mind.
• Silicon bring up expertise is very much sought after. FPGA board bring-up and emulation skills are good to have.
• Must be conversant with the following:
  • Verilog, System Verilog tools
  • Networking, and Interconnect Protocols experience, including PCI Express, 40/100G Ethernet, Fiber Channel, HT, sRIO, Interlaken, SAS is a plus.

Requirements

• 5+ years of Verification experience for SoCs
• Must have experience using SystemVerilog/Vera
• Strong experience creating self-checking testbench environments
• Strong experience writing test plans and testbench architecture
• Experience with Synopsys front end tools: i.e. DVE, VCS, or Cover Meter
• Networking protocols knowledge is a plus
• MSEE/CS minimum

Bandwidth Engine products from MoSys are memory dominated devices with ALUs and low-latency, high-bandwidth SerDes interfaces. This family of ICs is optimized for high-bandwidth, high-access rate applications such as networking, storage and video. Bandwidth Engine ICs include 576 Mb of memory and 10G SerDes I/O.

Responsibilities

• Work on verification infrastructure and testbenches, regressions and generation of directed and random tests for Bandwidth Engine products. The verification infrastructure is to be built ground-up to take advantage of automation at all levels - from test generation to test documentation.
• Module or unit-level testing will be a particular focus.
• An ideal candidate has a solid background in hardware verification and good experience in software and automation.

Requirements

• BSEE, MSEE or CS plus 10 years of relevant industry experience
• Solid experience in hardware verification, with excellent programming and scripting skiills
• Experience in Verilog, PERL, C required; C++ and TCL is preferred
• System Verilog/OVM experience is preferred
• Excellent team player, innovative and self-driven with good communication skills, including documentation

Verification of MoSys Bandwidth Engine device requires a knowledge of:

• Network packet and coding concepts
• High-speed SerDes links
• Error conditions on links and memories
• Highly-pipelined, high-speed designs
• ALU verification
• Processor verification

Responsibilities

• Design, implementation and verification of PCS/logical sublayer of interconnect IP such as SerDes and DDR
• Specification, micro-architecture, RTL design, synthesis, simulation, verification, automation and hardware/software debug
• Behavioral modeling of mixed-signal components of SerDes and memories
• Skills in modeling in C/C++, MATLAB and SystemVerilog desirable
• Work closely with other team for lab bringup, spec compliance and customer support is expected

• MSEE with 2 years or BSEE with at least 4 years of related work experience
• Verilog/SystemVerilog RTL, verification and modeling, Synopsys Design Compiler and Primetime (or equivalent)
• Scripting and automation skills -- Shell, PERL, TCL or Python
• C/C++, MATLAB or Python for signal processing is preferred
• Innovative, self driven team worker

Candidate will be responsible for technical support of MoSys Engineering and Applications team.

Responsibilities

• Si bringup of MoSys test chips, productsand customer chips
• Debug and characterize MoSys IP
• Stress the Si to identify strength and weaknesses on the IP
• Identify bugs, develop work around, propose solutions to designers
• Post process and parse data for results analysis
• Perform compliance testing for different high speed standards

Requirements

• B.S.E.E, past Lab experience in high speed SerDes, DDR and other interface protocols is essential
• System level understanding of applications such as networking, consumer electronics is preferred
• Familiarity to high speed standards such as PCI Express, 10GBASE-KR, XAUI, etc. are preferred
• Some level of expertise in scripting languages such as PERL or TCL is expected
• Excellent verbal and written communication skills
• Candidate must be organized, self-motivated, pro-active and have an eye for detail

• Development and maintenance of code for the on-chip microcontroller, BIST engine and development of FPGA code blocks for internal and external users of Bandwidth Engine memory ICs.
• Delivery of working ATE test vectors for the on-chip microcontroller code.
• Delivery of FPGA Verilog code blocks verified in Laboratory hardware.
• Candidate will work closely with Design Engineering to transfer engineering support of Bandwidth Engine products as they transition from design to manufacturing.  

• Solid grasp of digital design principles.
• Experience and ability to maintain/develop assembly language code base.
• Knowledge of register-level and assembler-level knowledge of microcontroller programming.
• Experience in using Altera or Xilinx FPGA design tools.
• Experience and proficient in Verilog, Tcl, and either Perl or Python.
• Strong problem-solving skills.
• Familiarity with ATPG tools such as TetraMAX or TestKompress is a very strong plus.
• ATE test background, particularly Verigy83K and 83K background a very strong plus.

• MSEE or MS Computer Engineering with applicable mix of courses in IC design, Logic Design, Computer Architecture and HDL. BSEE or BS Computer Engineering is acceptable if candidate can demonstrate equivalent knowledge in the breadth of Engineering disciplines covered by a MS program.
• Generally speaking, minimum five years of IC industry experience in areas related to Job Specification are expected. However, the number of years is not as important as demonstration of the variety of skills stated in job specification.