GigaChip Interface Enables Unparalleled Memory Capabilities in 100G and Beyond Networking Equipment
As networking equipment transitions from 10G to 40G to 100G and beyond, greater access to memory is increasingly required to execute complex packet header processing operations for line rate switching, routing, monitoring and security. Programmable logic devices from Tabula offer substantial on-chip bandwidth and off-chip memory capacity using commodity external memory. However, traditional memory solutions lack sufficient access to memory, exposing a bottleneck which strangles the overall system performance. Using MoSys® Bandwidth Engine® serial memory solutions combined with the highly efficient GigaChip Interface alleviates this chokepoint in the system by providing four times the access performance of traditional memory solutions.
Increased performance and bandwidth in the system are critical in order to meet the requirements for cutting-edge networking equipment. But, if the packet processors cannot access memory at the rates required, then the overall system performance suffers," stated
MoSys Bandwidth Engine solution provides high-access rates to high-speed memory using the GigaChip Interface and can accelerate performance by more than 4 times through intelligent offload of counters, metering functions, semaphores and transactional memory operations for link-list management. These types of intelligent offload capabilities enable high-bandwidth, high-efficiency chip-to-chip communications necessary for high-performance switching, routing, monitoring and content processing functions.
"As a leading provider of breakthrough programmable logic solutions for todays most challenging 100G systems applications, Tabula is always looking for partnerships that offer our customers innovative, powerful solutions," said Alain Bismuth, Vice President of Marketing for Tabula. Through our support of
The GigaChip Interface (GCI) is a scalable, high-performance, serial protocol for chip-to-chip communications that is differentiated in efficiency and reliability, resulting in system level benefits of reduced power, cost and complexity. Current implementations built with compatible CEI-11G or XFI SerDes electrical transport standards deliver up to 144Gbps of full duplex data throughput using 16 SerDes lanes when running at a 10G rate. A key differentiator for the GCI protocol is high transport efficiency, even for small payloads. Alternative serial interfaces are typically less than 50 percent efficient when transferring 8B and 16B data, which means that they deliver less than half the performance at a given bandwidth. The combination of 90 percent transport efficiency, from small to large payloads, combined with power-efficient short-reach physical interconnect makes GCI ideal for co-processor, memory or multi-chip communication. The interface also includes CRC error detection and automatic error recovery provisions to meet the high reliability requirements of enterprise, service provider and mission-critical communications and compute applications. GCI is an open, royalty-free, interface specification designed for use with the MoSys Bandwidth Engine family of ICs and is suitable for any chip-to-chip interconnect.
Bandwidth Engine, the GigaChip logo and MoSys are registered trademarks of MoSys, Inc. in the US and/or other countries. GigaChip, LineSpeed and the MoSys logo are trademarks of MoSys, Inc. All other marks mentioned herein are the property of their respective owners.