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Event Calendar
Industry and MoSys events of interest to our customers, investors, analysts and press (for investor events, click here):
Events
Webcasts
Events
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DesignCon 2012
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DesignCon is renowned as being the premier event for the semiconductor and electronic design engineering community. The community relies on DesignCon to find out what the latest design technologies and developments are in the industry.
It is the largest meeting of board designers, and is the ONLY event to address chip design engineers’ chip/system/package challenges. |
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January 30, 2012 to February 02, 2012 |
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Santa Clara Convention Center
Santa Clara, California |
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Linley Tech Data Center Conference 2012
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What do trends like cloud computing, virtualization, and network convergence mean to your next design? Beyond buzzwords, these trends have very real implications for all types of data-center networking systems and servers. Attendees of the Linley Tech Data Center Conference will get help sorting out these questions as well as insights into the latest developments in Data Centers.
The two-day, single-track event is the only one of its kind focused on the processors, Ethernet switches, backplanes, and interconnects for data-center networking and servers. The Linley Group will open the conference with an overview of the market, technologies, equipment-design, and silicon trends for designers of data-center equipment. |
| Date: |
February 07, 2012 to February 08, 2012 |
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DoubleTree by Hilton Hotel San Jose
2050 Gateway Place
San Jose, CA 95110 |
| Comments: |
Don't miss the presentation, "Behavioral Profiling: Not just for TSA" as presented by Michael J Miller, VP of Technology Innovation for MoSys.
Abstract: Data center security relies heavily on knowledge set, deep packet content analysis and extensive tracking of packet flows enabled by high performance memory solutions. Using current memory technologies, nearly 1000 pins and >15W are required to perform both inspection and tracking functions. Innovative solutions must be found to manage the pin count, power and board area. This presentation discussed MoSys’ Bandwidth Engine® Family of ICs, which address these issues with serial interfaces for 100G networking equipment.
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Webcasts
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WEBCAST: Meeting Chip to Chip I/O Demands of 100G & Beyond Line Cards
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If you missed this technical panel discussion at DesignCon 2011, it is not too late to explore trends and alternative solutions for interconnecting chips on 100 Gbps & beyond line cards that maximize throughput while minimizing pin count, die area and power. |
| Date: |
December 30, 2011 |
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Webcast will be available until 12/2011. |
| Comments: |
Join MoSys, Avago Technologies, Cadence Design Systems, Xilinx and Infonetics Research for a panel discussion: Meeting chip to chip I/O demands of 100G & beyond line cards
With more line card designs focusing on how to achieve packet forwarding beyond 100 Gbps, the bandwidth density of the card is increasing. At the same time the interface between devices on the line card such as the NPU, memory and communication interface is becoming more challenging. Traditional DDR/QDR single ended interfaces will become extremely challenging to design with beyond the 2.133 GHz because of pin counts, tight layout and timing constraints. As a result designers need to rethink packet processing and memory subsystems, the division of labor and the interconnect topology. Increasingly, serial interfaces are being considered as an alternative to parallel to traditional parallel busses to memory and co-processors. This panel will explore trends and alternatives solutions for interconnecting chips on 100 Gbps & beyond line cards that maximize throughput while minimizing pin count, die area and power.
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