Santa Clara Convention Center
Santa Clara, California
Memories for Extreme Networking to be presented by MoSys' Directof of IC Marketing, Michael Sporer, during Track 2, Infrastructure and Networking.
Abstract: Designers of networking equipment have had commodity DRAM, on-chip embedded SRAM and everything in between in order to meet extreme performance requirements. The award winning platforms use a combination of memory technologies from high bandwidth and high capacity DRAM for packet buffering as well as both on-chip and off-chip memory solutions for packet header processing. Switch chips that limit themselves to only on-chip memory are suitable for Layer 2 or top-of-rack type switches. In order to go beyond this application space requires memory capacity larger than can be economically deployed on-chip, and once the decision is made to use external memories the on-chip memory can be reduced which in turn enables more silicon area available for value-add functionality. In addition to commodity DRAM for packet buffering, extreme networking equipment traditionally utilized external SRAM, low latency DRAM and content addressable memories (CAM) all of which have connected to the host with a parallel interface. Extreme networking including SDN and NFV, is moving towards higher performance and more highly segmented memory architectures which utilize a serial interface. Further enhancements towards ‘smart memories’ which offload memory intensive operations from the host, including statistics, accounting and search functions enable next generation extreme networking equipment to be able to guarantee quality of service and monetize network bandwidth effectively.
The Linley Tech Processor Conference is The Linley Group's largest event and includes dual-track presentations on the latest processor chips, processor IP and other technology required to efficiently process packets of information in enterprise and carrier applications. Additional topics may include security and high-performance memories for networking.
Trade-Offs of a Coprocessing Engine vs. Fixed-Memory TCAM to be presented by MoSys VP of Technology Innovation and System Applications, Michael Miller in Track B, Session 4 on Wednesday October 22.
Abstract: With the number of networked things exploding, and with growing power constraints, architectures need to leverage flexible algorithms fueled by high-capacity, high-rate memory to deliver high-performance SDN and NFV systems. Existing solutions such as TCAMs are power hungry and size challenged. This presentation discusses a monolithic offload engine with 1Gb of memory capable of 12 billion transactions per second and macro processor engines that perform index-table accesses, semaphores, statistics, flow caches, hash tables, LPM, and ACLs supporting 400-gigabit systems and beyond.
This event will highlight the key technologies for next-generation networks and the components that will enable them. The event will be of interest not only to network equipment manufacturers and service providers, but also to investors and semiconductor suppliers.
Data Center Interconnects (Panel 2) with MoSys Panelist: John Monson
Panel description: Server performance and data center network traffic are growing dramatically. The traditional data center network architecture is being challenged by innovative approaches using both standardized and proprietary interconnects between servers and switches, and within the systems. New solutions and technologies becoming available include new modulations, high speed copper interconnects and silicon photonics. Solutions are being developed to support low cost 100G optical links up to 2km and optical connections within systems. 28 Gbit/s serial links over backplanes and to optical modules are also becoming available and the next generation currently in development will support 56 Gbit/s. This session will cover the latest developments, including data center architectures and the technologies and components for competing optical and copper interconnects.