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Abstract

The performance potential of TSV based DRAM stacks can be realized with two very different interface and packaging solutions. In the near term either a multi-chip, 2.5D packaging for High Bandwidth Memory (HBM) with a evolutionary, wide, parallel interface, or a discrete packaged device such as the Hybrid Memory Cube with a high performance serial interface. Both solutions have their place in new systems design and there are advancements in both options on the horizon.

There are technical tradeoffs but there are also important differences in commercial and economic factors, supply chain and manufacturing. Traditional memory interfaces are purpose built for only one or possibly two technologies whereas industry standard SerDes are much more adaptable to a variety of applications. The most significant issues and the ultimate decision driving factors depend on the host device that the memory is connected to and how that host device is integrated into the overall system.

This paper will also present the tradeoffs between the current and future of parallel versus serial interface for memory interconnect. We will examine tradeoffs between:

  • How scalable does the host IC need to be with respect to system performance?
  • Power / Thermal / Thermal Density
  • Raw Performance / Application specific performance
  • Package Size / Ball pitch / L2 Assembly Technology
  • Volume / Cost / Supply Chain / Multi-vendor
  • Packaging – when will 2.5D go to 3D?
  • Manufacturing – MCM yield efficiencies
  • Supply Chain – who owns the yield loss for MCMs?
  • Test Strategies / Yield / Rework
  • Quality / Reliability / Repair

We will also examine future interface trends:

  • Parallel Interface evolution – faster, wider  How long can this Last?
  • Serial Interface evolution – NRZ  PAM4  emerging
  • Interface efficiency – HMC vs. GCI vs. ILA
  • Standards based solutions vs. proprietary
  • Purpose built vs. Fungible IO

Based on experience at MoSys developing and introducing the GigaChip interface and 1st, 2nd and 3rd generations of Bandwidth Engine ICs and comparisons to anecdotal feedback regarding competing solutions the product definition of our next generation HBM based solution will be described and why we reached the conclusions that we did.