Author: Michael Miller, VP of Technology Innovation & System Applications
Abstract: As designers develop 400Gbps line cards and consider 1Tbps designs, serial interfaces will play dominant roles. At 400G, the traditional packet processing models are broken. High-performance-serial networking memories, gearboxes, and nx25G retimers will emerge to address 1Tbps ecosystem requirements. Pin I/O efficiency, reach and functionality are critical to deliver performance and manage interconnect, package and power limitations. This presentation will explore line-card architecture from a serial-interface devices (datapath & look-aside) perspective and the ramifications as they evolve towards 1Tbps.