Editor’s Note: In this Product How-To, Michael Miller of MoSys describes the challenges faced on the wired Internet backbone as increased network line and packet rates cause throughput bottlenecks at the processor/external DDR memory interface. He then shows how a new serial chip-to-chip protocol the company has developed, called the GigaChip Interface (GCI), with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate such bottle necks.